//--------------------------------------------------------------------
//		Timescale
//		Means that if you do #1 in the initial block of your
//		testbench, time is advanced by 1ns instead of 1ps
//--------------------------------------------------------------------
`timescale 1ns / 1ps
//--------------------------------------------------------------------

//--------------------------------------------------------------------
//		The Lab4FSM Testbench. You will need to write this entire
//		testbench on your own. Use Lab4BasicTestbench as an example.
//--------------------------------------------------------------------
module ALUtest();

	//----------------------------------------------------------------
	//		Parameters
	//----------------------------------------------------------------
	parameter HalfCycle		= 5;			//Half of the Clock Period is 5 ns
	//----------------------------------------------------------------

	//----------------------------------------------------------------
	//		Constants
	//----------------------------------------------------------------
	localparam Cycle		= 2*HalfCycle;	//The length of the entire Clock Period
	//----------------------------------------------------------------

	/* You will need to write everything else on your own */	

	//----------------------------------------------------------------
	//		Test Stimulus
	//----------------------------------------------------------------
	
	reg Clock;
	reg Reset;
	reg In, expected;
	
	wire Out;
	
	reg [31:0] A, B, Expected;
	reg [2:0] Control;
	wire [31:0] Result;
	wire Zero;
	
	initial Clock	= 0;				//Clock is at 0 at time 0 of the simulation
	always #(HalfCycle) Clock = ~Clock;	//Every half of a Clock period, flip the Clock
	ALU alutest(.A(A), .B(B), .Control(Control), .Result(Result), .Zero(Zero));
	
	
	initial begin
		#(10*Cycle);	//PLEASE LEAVE THIS HERE! This is required because the
						//simulation model of an FDRSE flip flop will not respond
						//to any inputs for the first 100ns of simulation
		
		
		
		
	/* You will need to complete this section on your own */
	
	end
	//----------------------------------------------------------------


endmodule
